Qwen3-Coder 30B-A3B-Instruct / ROCm 6.4.0, build unknown / FA on / PP512 TG128

Historical first-party llama-bench measurements by robustonian (display name 金のニワトリ), published August 2025, inspected October 13, 2026. Source's EVO-X2 section updated August 3, 2025. Exact measurement timestamp is not published. This report covers only ROCm, Flash Attention on, on the EVO-X2. It does not combine the source's Mac Studio, CPU-only, RTX 3060 or RTX 3090 measurements. No local benchmark rerun. Hardware: EVO-X2 with AMD Ryzen AI Max+ 395, integrated Radeon 8060S / gfx1151, 128 GB unified installed memory. Source explicitly enumerates exactly one ROCm GPU in this benchmark invocation and the native output binds backend ROCm and ngl=100. This establishes one participating iGPU rather than inferring GPU quantity from one host or a model name. GPU core/CU count, physical CPU-core count, clock, TDP, thermal conditions and per-run memory usage are not measured in this log. 128 GB is installed unified RAM, not dedicated VRAM or resident model allocation. Native model size 16.45 GiB is the GGUF tensor/model footprint, not measured RAM use. Model: Qwen3-Coder-30B-A3B-Instruct, source-linked Unsloth GGUF artifact Qwen3-Coder-30B-A3B-Instruct-UD-Q4_K_XL.gguf. Preserve exact UD-Q4_K_XL identity; llama-bench's coarse model description is qwen3moe 30B.A3B Q4_K - Medium, 30.53 B total parameters. A3B is the family active-parameter label, not a measurement of activated weights. Current matching artifact metadata at HF revision b17cb02dd882d5b6ab62fc777ad2995f19668350: 17,665,334,432 bytes; LFS SHA256 2841aa314d916434860cfb8990347528dcdfe5c350dbcb9d1461dbee88ff2533. Current size is consistent with the source's rounded 16.45 GiB, but source did not publish a historical file hash or HF snapshot. This current reference is not claimed to be the tested historical bytes. No weights downloaded. Source-native rates, tokens/s (published value +/- printed deviation): headline pp512 401.48 +/- 2.72; separate tg128 65.93 +/- 0.18. Longer tests in the same backend/FA arm: pp8192 383.41 +/- 0.46; separate tg8192 63.27 +/- 0.17. These are separate native prefill and generation microbenchmarks, not an input prompt followed by a same-request answer, and tg8192 is not decode after a prefilled 8192-token prompt. Neither rate is derived from request time or TTFT. No TTFT is published or calculated. Native test labels identify executed fixed-count token work; these are synthetic benchmark token evaluations, not verified natural-language output tokens. Runtime: source explicitly labels ROCm 6.4.0, native ROCm backend, device0 AMD Radeon Graphics gfx1151 (0x1151), VMM no, wave size32; GGML_CUDA_FORCE_MMQ=no and GGML_CUDA_FORCE_CUBLAS=no are HIP/CUDA-compatibility diagnostic labels, not proof of a separate NVIDIA device. The shown command is llama-bench -m [exact named artifact] -ngl100 -fa0,1. Source omits the ROCm executable's llama.cpp build hash and build number. The long table does not repeat its command line or device enumeration; its same-machine/backend binding comes from continuity within the EVO-X2 ROCm6.4.0 section, rather than an independent second startup receipt. The Vulkan6060 or CUDA6068 hashes on this same page must not be inherited into this ROCm arm. Exact repetitions, batch/microbatch, KV dtype, effective context allocation, CPU threads, warmup and timing implementation therefore remain unverified for ROCm; the printed plus/minus values are retained without inventing their sample count. The native pp512/tg128/pp8192/tg8192 labels and phase rates are directly published, not independently reconstructed. Read this as a source-native result with incomplete runtime reproducibility. No quality test or natural-language output transcript is provided. The earlier introductory claim that HIP was untested is superseded by the explicitly labeled ROCm6.4.0 addendum, which contains these results. Sources: https://zenn.dev/robustonian/scraps/445f2143217f75#comment-ce5cc183b8f0cf https://huggingface.co/unsloth/Qwen3-Coder-30B-A3B-Instruct-GGUF/blob/b17cb02dd882d5b6ab62fc777ad2995f19668350/Qwen3-Coder-30B-A3B-Instruct-UD-Q4_K_XL.gguf https://huggingface.co/Qwen/Qwen3-Coder-30B-A3B-Instruct The form rounds the structured PP/TG rates to one decimal; the exact source values are retained above.